1. Field of the Invention
The present invention relates to a memory analyzing apparatus, and more specifically to a structure of an apparatus for analyzing memory defects and for effectively remedying defective memory cells at high speed.
2. Description of the Prior Art
With increasing capacity of the memory device, a possibility of the memory device including defective memory cells increases, so that it has become difficult to maintain a high yield of the memory device. To overcome this problem; that is, to improve the yield of the memory device, it has become usual to remedy memory device by replacing a defective memory cell with another normal memory cell.
The usual memory device, for instance, DRAM or SRAM comprises, as shown in FIG. 12, an X address decoder 11 for decoding X addresses (column addresses) arranged in the X direction (row direction) and a Y address decoder 12 for decoding Y addresses (row addresses) arranged in the Y direction (column direction). Therefore, data can be written or read in or from the memory device by selecting some of the memory cells (or memory elements) 15 arranged in a matrix pattern.
Further, in order to remedy defective cells, a line having a defective cell is replaced with one of remedy lines (spare lines) for each appropriate defect remedy unit region 10. The spare lines are composed of column spare lines 16 and row spare lines 17, and these spare lines are arranged in each of the X and Y directions. Further, each spare line can be selected by an X spare (column spare) decoder 13 and a Y spare (row spare) decoder 14, respectively.
In the construction as described above, when a defective cell exists in a column line of the memory cell 15, this column line is replaced with a column spare line 16; and when a defective cell exists in a row line of the memory cell 15, this low line is replaced with a row spare line 17, both as shown by two arrows A and B in FIG. 12.
Here, when the defective cells of the memory cells 15 are replaced with the remedy lines 16 and 17, the line replacement is usually designated by cutting off a fuse.
Here, the method of remedying the defective cells of the memory device differs according to the distribution of the defective cells. Therefore, it is known that the remedy methods and systems have been so far discussed in various ways. Here, however, the procedure of how to remedy the defective cells of the memory cells 15 has become complicated more and more with increasing capacity of the memory device, so that it is usual to use a remedy analysis apparatus, in addition to a memory test body.
FIG. 13 is a block diagram showing a prior art memory analyzing apparatus for realizing the memory remedy function. As shown in FIG. 13, a defect cell memory 3 is provided in a memory tester body 1. In this defect cell memory 3, a defective cell status of a memory cell to be tested is stored. On the other hand, a remedy analyzing apparatus 2 is provided with a memory 4 connected to the defect cell memory 3. Further, the defect cell memory 3 of the memory tester body 1 and the memory 4 of the remedy analyzing apparatus 2 are so constructed as to be accessed at the same time by use of an address counter 6. Data of the defect cell memory 3 are written in the memory 4, and the written data are analyzed by a plurality of CPUs 5.
The operation of the above-mentioned prior art memory analyzing apparatus will be explained hereinbelow. First, the data of the defect cell memory 3 are read in sequence by activating an address counter 6, and the read data are written in the memory 4 of the remedy analyzing apparatus 2.
Further, the defect data of the memory cells are obtained by checking whether the contents of the memory 4 are normal or abnormal by use of the plural CPUs 5. Further, a memory remedy solution can be obtained on the basis of the obtained defect data.
Here, the case as shown in FIG. 14 will be considered by way of example, in which a defect remedy unit region 10 of one memory is shown. In FIG. 14, when defective cells are seen in the row line direction, there are four defective cells (shown by x) as A1, A2; A3; A4; and A5. Further, when seen in column line direction, there are three defective cells (shown by x) as A1, A3; A5; A2; and A4;
In this case, the cells are not simply remedied, but the remedy lines are decided by checking the distribution of the defective cells A1, A2, A3, A4 and A5.
For instance, although the column addresses of the two defective cells A1 and A2 are different from each other, since the row address of these two defective cells A1 and A2 is the same, these two defective cells A1 and A2 can be remedied by use of only one common remedy line (the row address is R1) of the row spare lines 17.
On the other hand, although the column address of the defective cell A4 is the same as that of the defective cell A2, in this case, these two defective cells A4 and A2 are remedied by use of another remedy line (the row address is R2) of the row spare lines 17.
Further, although the column address of the defective cell A3 is the same as that of the defective cell A1, the defective cell A1 has been already remedied by the other spare remedy line (the row address is R1) of the row spare lines 17. Further, in this case, the defective cell A3 is remedied by a spare remedy line (the column address is C1) of the column spare lines 16.
Further, the defective cell A5 is remedied by another spare remedy line (the column address is C2) of the column spare lines 16.
As a result of the above-mentioned remedy, however, there exists a case where a defective cell A6 is newly added by the spare remedy line (the designated row address is R1) of the row spare lines 17. In this case, however, since the column address C2 of this defective cell A6 is the same as the column address C2 of the defective cell A5, it is possible to remedy this defective cell A6 by the column direction remedy line (the column address is C2) of the column spare lines 16.
As a result, the six defective cells A1 to A6 can be remedied by use of the two column lines (the column addresses are C1 and C2) and the two row lines (the row addresses are R1 and R2), that is, by use of four remedy lines in total.
In this case, however, as the defective cell remedy method, many combinations of various sorts can be considered by use of the column spare lines and the row spare lines. In addition, when the other defective cells are newly added by the row and column spare remedy lines, the combinations of the column and row spare lines are further complicated.
In the prior art memory analyzing apparatus as described above, the construction for remedying defective cells is such that: defective cells are detected for each defect remedy unit region 10; the remedy lines designated by the row addresses and column addresses are determined in correspondence to the defective cells. Therefore, although there exists such an advantage that one memory remedy unit region can be processes as a single block at high processing speed by a CPU 5, since it has been necessary to provide the memory 4 having the same capacity scale as that of the defect cell memory 3, in the memory remedy analyzing apparatus, there exists a problem in that the cost of the memory analyzing apparatus increases.
In addition, in the case of the large-capacity memory device, it is difficult to collect data including the defective cells existing on the remedy (spare) line as a block. In other words, when defective data are collected at the CPU 5 and then arranged so as to be analyzed and remedied easily, the data transfer between the memory 4 and the CPU 5 inevitably increases. Further, since the data arrangement is not regular, there arises another problem in that the processing time becomes markedly long.
In the case of the example as shown in FIG. 15, for instance, when five defective cells A1 to A5 are represented by use of R (row) and C (column), there exists six combinations of C-C-R-R sequence, C-R-C-R sequence, C-R-R-C sequence, R-R-C-C sequence, R-C-R-C sequence, and R-C-C-R sequence. Therefore, all the defective cells A1 to A5 must be decided, for each column remedy (spare) line and for each row remedy (spare) line, as to whether these defective cells can be remedied or not or as to whether there exists an effective remedy method or not, on the basis of trial and error method, in the sequence of the above six combinations, so that a huge analysis processing time is needed. Here, since this processing time increases acceleratively with increasing number of the defective cells, when the memory capacity is large, the analyzing time exerts a serious influence upon the manufacturing productivity of the memory device.
Further, as shown in FIG. 16, for instance, in the defect cell memory 3, even if the defective cells are arranged regularly as a sequence of a main cell, a row spare cell, a main cell, a column spare cell, . . . in the address direction, when these cells are read by the CPU 5 in practice, since the main cell portions and the respective row and column remedy portions are not arranged regularly, a long analyzing time is required for the CPU 5.
Further, in order to shorten the processing time, as shown in FIG. 17, it may be possible to consider such a method of increasing the total productivity by providing two defect cell memories 3 in the memory tester body 1. In this case, when one defect cell memory 3 is being used by the memory tester body, the other defect cell memory 3 is used by the remedy analyzing apparatus 2. In this method, however, there arises another problem in that the cost of the memory analyzing apparatus increases with increasing capacity of the defect cell memory 3.
As described above, in the prior art memory analyzing apparatus, since the memory remedy method has been complicated more and more with increasing capacity of the memory device, an extremely long time has been required to analyze how to remedy the defective cells. Further, since this remedy analysis is executed simultaneously with the general memory test, it is essential to shorten this remedy analysis time in order to shorten the memory test time; that is, to improve the memory productivity.